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IN90S2333DW, IN90LS2333DW,
8-BIT MICROCONTROLLER WITH 2K/4K BYTES BUILD-IN PROGRAMMABLE FLASH
Description
The IN90S2333 is a low-power CMOS 8-bit microcontroller based on the AVR RISC architecture. By 28 executing powerful instructions in a single clock cycle, the IN90S2333 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed.
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The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers. The AT90S2333/4433 provides the following features: 2K/4K bytes of In-System Programmable Flash, 128/256 bytes EEPROM, 128 bytes SRAM, 20 general purpose I/O lines, 32 general purpose working registers, two flexible timer/counters with compare modes, internal and external interrupts, a programmable serial UART, 6-channel, 10-bit ADC, programmable Watchdog Timer with internal oscillator, an SPI serial port and two software selectable power saving modes. The Idle mode stops the CPU while allowing the SRAM, timer/counters, SPI port and interrupt system to continue functioning. The Power Down mode saves the register contents but freezes the oscillator, disabling all other chip functions until the next interrupt or hardware reset. The device is manufactured using Atmel's high density nonvolatile memory technology. The on-chip Flash program memory can be reprogrammed in-system through an SPI serial interface or by a conventional nonvolatile memory programmer. By combining a RISC 8-bit CPU with In-System Programmable Flash on a monolithic chip, the Atmel AT90S2333/4433 is a powerful microcontroller that provides a highly flexible and cost effective solution to many embedded control applications. The AT90S2333/4433 AVR is supported with a full suite of program and system development tools including: C compilers, macro assemblers, program debugger/simulators, in-circuit emulators, and evaluation kits.
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IN90S2333DW, IN90LS2333DW,
Features
* High-performance and Low-power AVR(R) 8-bit RISC Architecture - 118 Powerful Instructions - Most Single Cycle Execution - 32 x 8 General Purpose Working Registers - Up to 8 MIPS Throughput at 8 MHz * Data and Nonvolatile Program Memory - 2K/4K Bytes of In-System Programmable Flash Endurance 1,000 Write/Erase Cycles - 128 Bytes of SRAM - 128/256 Bytes of In-System Programmable EEPROM Endurance: 100,000 Write/Erase Cycles - Programming Lock for Flash Program and EEPROM Data Security * Peripheral Features - One 8-bit Timer/Counter with Separate Prescaler - Expanded 16-bit Timer/Counter with Separate Prescaler, Compare, Capture Modes and 8-, 9- or 10-bit PWM - On-chip Analog Comparator - Programmable Watchdog Timer with Separate On-chip Oscillator - Programmable UART - 6-channel, 10-bit ADC - Master/Slave SPI Serial Interface * Special Microcontroller Features - Brown-Out Reset Circuit - Enhanced Power-on Reset Circuit - Low-Power Idle and Power Down Modes - External and Internal Interrupt Sources * Specifications - Low-power, High-speed CMOS Process Technology - Fully Static Operation * Power Consumption at 4 MHz, 3V, 25oC - Active: 3.4 mA - Idle Mode: 1.4 mA - Power Down Mode: <1 A * I/O and Packages - 20 Programmable I/O Lines - 28-pin PDIP and 32-pin TQFP * Operating Voltage - 2.7V - 6.0V (IN90LS2333) - 4.0V - 6.0V (IN90S2333 ) * Speed Grades - 0 - 4 MHz (IN90LS2333 ) 0 - 8 MHz (IN90S2333 )
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IN90S2333DW, IN90LS2333DW,
Block Diagram
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IN90S2333DW, IN90LS2333DW,
Pin Descriptions
VCC Supply voltage GND Ground Port B (PB5..PB0) Port B is a 6-bit bi-directional I/O port with internal pullup resistors. The Port B output buffers can sink 20 mA. As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated. Port B also serves the functions of various special features of the IN90S2333. The port B pins are tristated when a reset condition becomes active, even if the clock is not running. Port C (PC5..PC0) Port C is a 6-bit bi-directional I/O port with internal pullup resistors. The Port C output buffers can sink 20 mA. As inputs, Port C pins that are externally pulled low will source current if the pull-up resistors are activated. Port C also serves as the analog inputs to the A/D Converter. The port C pins are tristated when a reset condition becomes active, even if the clock is not running. Port D (PD7..PD0) Port D is an 8-bit bi-directional I/O port with internal pull-up resistors. The Port D output buffers can sink 20 mA. As inputs, Port D pins that are externally pulled low will source current if the pull-up resistors are activated. Port D also serves the functions of various special features of the IN90S2333 The port D pins are tristated when a reset condition becomes active, even if the clock is not running. RESET Reset input. An external reset is generated by a low level on the RESET pin. Reset pulses longer than 50 ns will generate a reset, even if the clock is not running. Shorter pulses are not guaranteed to generate a reset. XTAL1 Input to the inverting oscillator amplifier and input to the internal clock operating circuit. XTAL2 Output from the inverting oscillator amplifier AVCC via a low-pass filter. See This is the supply voltage pin for the A/D Converter. It should be externally connected to VCC Datasheet for details on operation of the ADC. AREF This is the analog reference input for the A/D Converter. For ADC operations, a voltage in the range 2.7V to AVCC must be applied to this pin.
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IN90S2333DW, IN90LS2333DW,
AGND If the board has a separate analog ground plane, this pin should be connected to this ground plane. Otherwise, connect to GND.
Architectural Overview
The fast-access register file concept contains 32 x 8-bit general purpose working registers with a single clock cycle access time. This means that during one single clock cycle, one Arithmetic Logic Unit (ALU) operation is executed. Two operands are output from the register file, the operation is executed, and the result is stored back in the register file - in one clock cycle. Six of the 32 registers can be used as three 16-bits indirect address register pointers for Data Space addressing - enabling efficient address calculations. One of the three address pointers is also used as the address pointer for the constant table look up function. These added function registers are the 16-bits Xregister, Y-register and Z-register. The ALU supports arithmetic and logic functions between registers or between a constant and a register. Single register operations are also executed in the ALU. In addition to the register operation, the conventional memory addressing modes can be used on the register file as well. This is enabled by the fact that the register file is assigned the 32 lowermost Data Space addresses ($00 - $1F), allowing them to be accessed as though they were ordinary memory locations.
AVR IN90S2333 Architecture
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IN90S2333DW, IN90LS2333DW,
The I/O memory space contains 64 addresses for CPU peripheral functions as Control Registers, Timer/Counters, A/D-converters, and other I/O functions. The I/O Memory can be accessed directly, or as the Data Space locations following those of the register file, $20 - $5F. The AVR uses a Harvard architecture concept - with separate memories and buses for program and data. The program memory is executed with a two stage pipeline. While one instruction is being executed, the next instruction is pre-fetched from the program memory. This concept enables instructions to be executed in every clock cycle. The program memory is In-System Programmable Flash memory. With the relative jump and call instructions, the whole 1K/2K word address space is directly accessed. Most AVR instructions have a single 16-bit word format. Every program memory address contains a 16or 32-bit instruction. During interrupts and subroutine calls, the return address program counter (PC) is stored on the stack. The stack is effectively allocated in the general data SRAM, and consequently the stack size is only limited by the total SRAM size and the usage of the SRAM. All user programs must initialize the SP in the reset routine (before subroutines or interrupts are executed). The 8-bit stack pointer SP is read/write accessible in the I/O space. The 128 bytes data SRAM can be easily accessed through the five different addressing modes supported in the AVR architecture. The memory spaces in the AVR architecture are all linear and regular memory maps.
Memory Map
A flexible interrupt module has its control registers in the I/O space with an additional global interrupt enable bit in the status register. All the different interrupts have a separate interrupt vector in the interrupt vector table at the beginning of the program memory. The different interrupts have priority in accordance with their interrupt vector position. The lower the interrupt vector address, the higher the priority.
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IN90S2333DW, IN90LS2333DW,
Register Summary
Address
$3F ($5F) $3E ($5E) $3D ($5D) $3C ($5C) $3B ($5B) $3A ($5A) $39 ($59) $38 ($58) $37 ($57) $36 ($56) $35 ($55) $34 ($54) $33 ($53) $32 ($52) $31 ($51) $30 ($50) $2F ($4F) $2E ($4E) $2D ($4D) $2C ($4C) $2B ($4B) $2A ($4A) $29 ($49) $28 ($48) $27 ($47) $26 ($46) $25 ($45) $24 ($44) $23 ($43) $22 ($42) $21 ($41) $20 ($40) $1F ($3F) $1E ($3E) $1D ($3D) $1C ($3C) $1B ($3B) $1A ($3A) $19 ($39) $18 ($38) $17 ($37) $16 ($36) $15 ($35) $14 ($34) $13 ($33) $12 ($32) $11 ($31) $10 ($30) $0F ($2F) $0E ($2E) $0D ($2D) $0C ($2C)
Name
SREG Reserved SP Reserved GIMSK GIFR TIMSK TIFR Reserved Reserved MCUCR MCUSR TCCR0 TCNT0 Reserved Reserved TCCR1A TCCR1B TCNT1H TCNT1L OCR1H OCR1L Reserved Reserved ICR1H ICR1L Reserved Reserved Reserved Reserved WDTCR Reserved Reserved EEAR EEDR EECR Reserved Reserved Reserved PORTB DDRB PINB PORTC DDRC PINC PORTD DDRD PIND SPDR SPSR SPCR UDR
Bit 7
I SP7 INT1 INTF1 TOIE1 TOV1
Bit 6
T SP6 INT0 INTF0 OCIE1 OCF1
Bit 5
H SP5 -
Bit 4
S SP4 -
Bit 3
V SP3 TICIE1 ICF1
Bit 2
N SP2 -
Bit 1
Z SP1 TOIE0 TOV0
Bit 0
C SP0 -
-
SE -
SM -
ISC11 WDRF -
ISC10 BORF CS02
ISC01 EXTRF CS01
ISC00 PORF CS00
Timer/Counter0 (8 Bits)
COM1 1 ICNC1
COM10 ICES1
-
-
CTC1
CS12
PWM11 CS11
PWM10 CS10
Timer/Counter1 - Counter Register High Byte Timer/Counter1 - Counter Register Low Byte Timer/Counter1 - Output Compare Register High Byte Timer/Counter1 - Output Compare Register Low Byte
Timer/Counter1 - Input Capture Register High Byte Timer/Counter1 - Input Capture Register Low Byte
-
-
-
WDTOE
WDE
WDP2
WDP1
WDP0
EEPROM Address Register EEPROM Data Register EERIE EEMWE EEWE EERE
PORT D7 DDD7 PIND7 SPIF SPIE
PORTD6 DDD6 PIND6 WCOL SPE
PORTB5 DDB5 PINB5 PORTC5 DDC5 PINC5 PORTD5 DDD5 PIND5 DORD
PORTB4 DDB4 PINB4 PORTC4 DDC4 PINC4 PORTD4 DDD4 PIND4 MSTR
PORTB3 DDB3 PINB3 PORTC3 DDC3 PINC3 PORTD3 DDD3 PIND3 CPOL
PORTB2 DDB2 PINB2 PORTC2 DDC2 PINC2 PORTD2 DDD2 PIND2 CPHA
PORTB1 DDB1 PINB1 PORTC1 DDC1 PINC1 PORTD1 DDD1 PIND1 SPR1
PORTB0 DDB0 PINB0 PORTC0 DDC0 PINC0 PORTD0 DDD0 PIND0 SPR0
SPI Data Register
UART I/O Data Register
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IN90S2333DW, IN90LS2333DW,
Register Summary (Continued)
Address
$0B ($2B) $0A ($2A) $09 ($29) $08 ($28) $07 ($27) $06 ($26) $05 ($25) $04 ($24) $03 ($23) $02 ($22) $01 ($21) $00 ($20)
Name
UCSRA UCSRB UBRR ACSR ADMUX ADCSR ADCH ADCL UBRRHI Reserved Reserved Reserved
Bit 7
RXC RXCIE ACD ADEN ADC7
Bit 6
TXC TXCIE AINBG ADCBG ADSC ADC6
Bit 5
UDRE UDRIE ACO ADFR ADC5
Bit 4
FE RXEN ACI ADIF ADC4
Bit 3
OR TXEN ACIE ADIE ADC3
Bit 2
CHR9 ACIC MUX2 ADPS2 ADC2
Bit 1
RXB8 ACIS1 MUX1 ADPS1 ADC9 ADC1
Bit 0
TXB8 ACIS0 MUX0 ADPS0 ADC8 ADC0
UART Baud Rate Register
UART Baud Rate Register High
Notes: 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written. 2. Some of the status flags are cleared by writing a logical one to them. Note that the CBI and SBI instructions will operate on all bits in the I/O register, writing a one back into any flag read as set, thus clearing the flag. The CBI and SBI instructions work with registers $00 to $1F only.
Instruction Set Summary
Mnemonics Operands Description Operation Flags #Cloc ks
1 1 2 1 1 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 3 3 4 4 ARITHMETIC AND LOGIC INSTRUCTIONS ADD ADC ADIW SUB SUBI SBC SBCI SBIW AND ANDI OR ORI EOR COM NEG SBR CBR INC DEC TST CLR SER RJMP IJMP RCALL ICALL RET RETI k Rd, Rr Rd, Rr Rdl,K Rd, Rr Rd, K Rd, Rr Rd, K Rdl,K Rd, Rr Rd, K Rd, Rr Rd, K Rd, Rr Rd Rd Rd,K Rd,K Rd Rd Rd Rd Rd k Add two Registers Add with Carry two Registers Add Immediate to Word Subtract two Registers Subtract Constant from Register Subtract with Carry two Registers Subtract with Carry Constant from Reg. Subtract Immediate from Word Logical AND Registers Logical AND Register and Constant Logical OR Registers Logical OR Register and Constant Exclusive OR Registers One's Complement Two's Complement Set Bit(s) in Register Clear Bit(s) in Register Increment Decrement Test for Zero or Minus Clear Register Set Register Relative Jump Indirect Jump to (Z) Relative Subroutine Call Indirect Call to (Z) Subroutine Return Interrupt Return Rd Rd + Rr Rd Rd + Rr + C Rdh:Rdl Rdh:Rdl + K Rd Rd - Rr Rd Rd - K Rd Rd - Rr - C Rd Rd - K - C Rdh:Rdl Rdh:Rdl - K Rd Rd * Rr Rd Rd *K Rd Rd v Rr Rd Rd v K Rd Rd Rr Rd $FF - Rd Rd $00 - Rd Rd Rd v K Rd Rd * ($FF - K) Rd Rd + 1 Rd Rd - 1 Rd Rd * Rd Rd Rd Rd Rd $FF PC PC + k + 1 PC Z PC PC + k + 1 PC Z PC STACK PC STACK Z,C,N,V,H Z,C,N,V,H Z,C,N,V,S Z,C,N,V,H Z,C,N,V,H Z,C,N,V,H Z,C,N,V,H Z,C,N,V,S Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V Z,C,N,V Z,C,N,V,H Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V None None None None None None I
BRANCH INSTRUCTIONS
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IN90S2333DW, IN90LS2333DW,
Instruction Set Summary (Continued)
Mnemonics
CPSE CP CPC CPI SBRC SBRS SBIC SBIS BRBS BRBC BREQ BRNE BRCS BRCC BRSH BRLO BRMI BRPL BRGE BRLT BRHS BRHC BRTS BRTC BRVS BRVC BRIE BRID MOV LDI LD LD LD LD LD LD LDD LD LD LD LDD LDS ST ST ST ST
Operands
Rd,Rr Rd,Rr Rd,Rr Rd,K Rr, b Rr, b P, b P, b s, k s, k k k k k k k k k k k k k k k k k k k Rd, Rr Rd, K Rd, X Rd, X+ Rd, - X Rd, Y Rd, Y+ Rd, - Y Rd,Y+q Rd, Z Rd, Z+ Rd, -Z Rd, Z+q Rd, k X, Rr X+, Rr - X, Rr Y, Rr
Description
Compare, Skip if Equal Compare Compare with Carry Compare Register with Immediate Skip if Bit in Register Cleared Skip if Bit in Register is Set Skip if Bit in I/O Register Cleared Skip if Bit in I/O Register is Set Branch if Status Flag Set
OPERATION
if (Rd = Rr) PC PC + 2 or 3 Rd - Rr Rd - Rr - C Rd - K if (Rr(b)=0) PC PC + 2 or 3 if (Rr(b)=1) PC PC + 2 or 3 if (P(b)=0) PC PC + 2 or 3 if (P(b)=1) PC PC + 2 or 3 if (SREG(s) = 1) then PCPC+k + 1 if (SREG(s) = 0) then PCPC+k + 1 if (Z = 1) then PC PC + k + 1 if (Z = 0) then PC PC + k + 1 if (C = 1) then PC PC + k + 1 if (C = 0) then PC PC + k + 1 if (C = 0) then PC PC + k + 1 if (C = 1) then PC PC + k + 1 if (N = 1) then PC PC + k + 1 if (N = 0) then PC PC + k + 1 if (N if (N V= 0) then PC PC + k + 1 V= 1) then PC PC + k + 1
Flags
None Z, N,V,C,H Z, N,V,C,H Z, N,V,C,H None None None None None None None None None None None None None None None None None None None
#Cloc ks
1/2/ 3 1 1 1 1/2/ 3 1/2/ 3 1/2/ 3 1/2/ 3 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2
Branch if Status Flag Cleared Branch if Equal Branch if Not Equal Branch if Carry Set Branch if Carry Cleared Branch if Same or Higher Branch if Lower Branch if Minus Branch if Plus Branch if Greater or Equal, Signed Branch if Less Than Zero, Signed Branch if Half Carry Flag Set Branch if Half Carry Flag Cleared Branch if T Flag Set Branch if T Flag Cleared Branch if Overflow Flag is Set Branch if Overflow Flag is Cleared Branch if Interrupt Enabled Branch if Interrupt Disabled Move Between Registers Load Immediate Load Indirect Load Indirect and Post-Inc. Load Indirect and Pre-Dec. Load Indirect Load Indirect and Post-Inc. Load Indirect and Pre-Dec. Load Indirect with Displacement Load Indirect Load Indirect and Post-Inc. Load Indirect and Pre-Dec. Load Indirect with Displacement Load Direct from SRAM Store Indirect Store Indirect and Post-Inc. Store Indirect and Pre-Dec. Store Indirect
if (H = 1) then PC PC + k + 1 if (H = 0) then PC PC + k + 1 if (T = 1) then PC PC + k+ 1 if (T = 0) then PC PC + k + 1 if (V = 1) then PC PC + k + 1 if (V = 0) then PC PC + k + 1 if ( I = 1) then PC PC + k + 1 if ( I = 0) then PC PC + k + 1 Rd Rr Rd K Rd (X) Rd (X), X X + 1 X X - 1, Rd (X) Rd (Y) Rd (Y), Y Y + 1 Y Y - 1, Rd (Y) Rd (Y + q) Rd (Z) Rd (Z), Z Z+1 Z Z - 1, Rd (Z) Rd (Z + q) Rd (k) (X) Rr (X) Rr, X X + 1 X X - 1, (X) Rr (Y) Rr
None None None None None None None None None None None None None None None None None None None None None None None
1/2 1/2 1/2 1/2 1/2 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
DATA TRANSFER INSTRUCTIONS
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IN90S2333DW, IN90LS2333DW,
ST ST STD Y+, Rr - Y, Rr Y+q,Rr Store Indirect and Post-Inc. Store Indirect and Pre-Dec. Store Indirect with Displacement (Y) Rr, Y Y + 1 Y Y - 1, (Y) Rr (Y + q) Rr None None None 2 2 2
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IN90S2333DW, IN90LS2333DW,
Instruction Set Summary (Continued)
Mnemonics
ST ST ST STD STS LPM IN OUT PUSH POP SBI CBI LSL LSR ROL ROR ASR SWAP BSET BCLR BST BLD SEC CLC SEN CLN SEZ CLZ SEI CLI SES CLS SEV CLV SET CLT SEH CLH NOP SLEEP WDR Rd, P P, Rr Rr Rd P,b P,b Rd Rd Rd Rd Rd Rd s s Rr, b Rd, b
Operands
Z, Rr Z+, Rr -Z, Rr Z+q,Rr k, Rr
Description
Store Indirect Store Indirect and Post-Inc. Store Indirect and Pre-Dec. Store Indirect with Displacement Store Direct to SRAM Load Program Memory In Port Out Port Push Register on Stack Pop Register from Stack Set Bit in I/O Register Clear Bit in I/O Register Logical Shift Left Logical Shift Right Rotate Left Through Carry Rotate Right Through Carry Arithmetic Shift Right Swap Nibbles
OPERATION
(Z) Rr (Z) Rr, Z Z + 1 Z Z - 1, (Z) Rr (Z + q) Rr (k) Rr R0 (Z) Rd P P Rr STACK Rr Rd STACK I/O(P,b) 1 I/O(P,b) 0 Rd(n+1) Rd(n), Rd(0) 0 Rd(n) Rd(n+1), Rd(7) 0 Rd(0)C,Rd(n+1) Rd(n),CRd(7) Rd(7)C,Rd(n) Rd(n+1),CRd(0) Rd(n) Rd(n+1), n=0..6 Rd(3..0)Rd(7..4),Rd(7..4)Rd(3.. 0) SREG(s) 1 SREG(s) 0 T Rr(b) Rd(b) T C1 C0 N1 N0 Z1 Z0 I1 I 0 S1 S0 V1 V0 T1 T0 H1 H0 (see specific descr. for Sleep function) (see specific descr. for WDR/timer)
Flags
None None None None None None None None None None None None Z,C,N,V Z,C,N,V Z,C,N,V Z,C,N,V Z,C,N,V None SREG(s) SREG(s) T None C C N N Z Z I I S S V V T T H H None None None
#Cloc ks
2 2 2 2 2 3 1 1 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 3 1
BIT AND BIT-TEST INSTRUCTIONS
Flag Set Flag Clear Bit Store from Register to T Bit load from T to Register Set Carry Clear Carry Set Negative Flag Clear Negative Flag Set Zero Flag Clear Zero Flag Global Interrupt Enable Global Interrupt Disable Set Signed Test Flag Clear Signed Test Flag Set Twos Complement Overflow. Clear Twos Complement Overflow Set T in SREG Clear T in SREG Set Half Carry Flag in SREG Clear Half Carry Flag in SREG No Operation Sleep Watchdog Reset
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IN90S2333DW, IN90LS2333DW,
Package Overall Dimensions
D 28 15
e1
E
H
01
e
14 h x 45 A1 A 0.25 (0.010) M TC M L C
-TB
A
A1
B
C
D mm
E
e
e2
H
h
L
min max
2.35 3.05
0.05 0.35
0.35 0.50
0.14 0.32
17.7 18.5
8.23 8.90
1.27 (nom )
11.4 3 (nom )
11.5 12.7
0.25 0.75
0.40 1.27
deg ree 0 8
SO - package MS-013AE
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